Terasic DE0-Nano FPGA Development Board

Terasic Technologies introduced the DE0-Nano FPGA development and education board for prototyping circuit designs. The DE0-Nano board features an Altera Cyclone IV FPGA, 32 MB of SDRAM, 2 Kb EEPROM, 16 Mb serial configuration memory device, National Semiconductor 8-channel 12-bit A/D converter, Analog Devices 13-bit 3-axis accelerometer, built-in USB Blaster for FPGA programming, two push-buttons, eight user LEDs, four dip-switches, and expansion headers. Source code for the components on the FPGA board are also included.

Terasic Technologies DE0-Nano FPGA development and education board

DE0-Nano Development and Education Board Features

Altera Cyclone IV EP4CE22F17C6N FPGA
On-board USB-Blaster circuit for programming
Altera EPCS16 serial configuration device
Two 40-pin Headers (GPIOs) provides 72 I/O pins
Two 5V power pins, two 3.3V power pins and four ground pins
26-pin header provides 16 digital I/O pins and 8 analog input pins to connect to analog sensors
32MB SDRAM
2Kb I2C EEPROM
Eight green LEDs
Two debounced push-buttons
Four dip switches
ADI ADXL345 3-axis accelerometer with high resolution (13-bit)
National Semiconductor ADC128S022 8-Channel, 12-bit A/D Converter (50 ksps to 200 ksps)
On-board 50MHz clock oscillator
Power Supply: USB Type mini-AB port (5V), Two DC 5V pins of the GPIO headers (5V), 2-pin external power header (3.6-5.7V)
Source code for every component on board that enables users to quickly and easily gain an understanding of the basic design concepts